Timers

__**INTRODUCTION TO TIMERS :**__

A timer is just a specialized type of clock used to control the sequence of an event or a process.Timers are used everywhere like in watches where the minute hand continuously counts upto 60 and reset back to zero.The timer’s count gets incremented by one after increment of each clock pulse.The smallest time a timer can measure is equal to the time period of the clock it is working on. Just like the ADC operation, we need to change certain bit values in Timer registers.The maximum amount of count a timer can count upto depends upon the number of bits available to store in the counter value.

There are two timers available namely Timer A and timer B. We will be discussing Timer A at present.

__**Uses** :__

 * to perform a certain task at a specific interval of time or after specific periods of time.
 * to different waveforms of required frequencies (P.W.M.).
 * to read ADC values after certain intervals of time.All these can be done using timers.

__**Key features** :__

 * 16 bit Timer/counter
 * Four different operating modes(discussed in laer part of the tutorial)
 * Configurable outputs with P.W.M. capability
 * Interrupt generation capability

//**16 BIT TIMER/COUNTER :**// The number 16 bit stands for the maximum number of cycles a counter can store before resetting. Thus an 8 bit counter can store a maximum count of 1023 starting from 0 and a 16 bit counter can store a count of 65535 starting from 0. The 16 bit timer/counter register **TAR**(Timer A Register) increments or decrements depending on the selected mode with each rising edge of the clock signal. TAR can be read or written by the software. Furthermore, a timer can generate an interrupt if required.

__//**TIMER MODES :**//__

In the UP mode ,timer counts upto a particular value specified by the user according to the requirements. That value must be less than the maximum value a timer can store i.e. 65535.Therefore, the timer counts from 0 to lets say, x. So , the total number of counts is equal to x+1. As soon as the timer value exceeds the specified value, it starts counting from 0 again after resetting.
 * 1.UP MODE**

In continuous mode, the user does not define any specified value of counts. The timer continuously counts up to the maximum value and resets itself. The continuous mode can be used to generate independent time intervals and output frequencies.
 * 2.CONTINUOUS MODE**

In up/down mode, the user defines a certain value for the timer. The timer starts increments from 0 to that specified value and as soon as it reaches that value, it starts decrementing back to zero. Unless the modes described above it does not resets to zero after reaching a certain value.
 * 3.UP/DOWN MODE**

The timer is haulted.
 * 4. STOP**

//**HOW DO WE KNOW THAT THE COUNTER HAS COUNTED UP TO THE REQUIRED VALUE OF COUNTS ??**// Just like ADC conversion flag, timer has also an associated flag which changes its value at a certain point. In UP mode, **TAIFG**(Timer A Interrupt FlaG) is set when the timer counts from max. value specified to zero. Similarly in continuous mode, the flag value is set when the count value goes from max. value to zero..In UP/DOWN mode, The flag is set when couter reaches a value of 0 after decrementing from the maximum value.

Suppose you want to toggle an LED after each 5 seconds. You need to decide two things. firstly the frequency of the clock and secondly the number of clock cycles which make a total time of 5 seconds.Suppose we choose a clock of 1KHz frequencyand a divider of factor 1 .So, the time period is 1ms.So. to get a total of 5 seconds, we need a total of 5sec/0.001sec = 5000 counts. SO, with a clock of 1KHz and a count of 5000, we can do the blinking of LED. After each 5000 counts, the counter will reset itself and interrupt flag is set and we can toggle our LED at that point of time.If we use a divider of factor 2, the clock source frequency would become the half of the original frequency and the time would be doubled. Hence for this purpose, the timer should be used in UP mode and and a count value of 5000 should be specified through registers after clock source selection.
 * WHY CLOCK SOURCE SELECTION AND DIVIDER FACTOR SELECTION ARE SO IMPORTANT HERE ???**

**KEY STEPS** :

 * Select a Clock source and a divider factor according to the purpose
 * Select a mode for the timer like UP mode or continuous mode
 * Selct a maximum value for the counter
 * Read the value of the count at any point of time and do the required task
 * See the change in the value of the flag as an indication of counter reset
 * Use interrupts (if necessary)

There are three main registers which are required fior the time being. a. **TAR(**Timer A Register)
 * //TIMER Registers// :**

b. **TACTL**(Timer A Control register)

c. **TACCR**(Timer A capture/Compare register)


 * TACTL register settings** :
 * Clock source : **TASSEL** bits ---

00 =>TACLK

01 =>ACLK

10 => SMCLK

11 =>INCLK (see the device specific data sheet)

Suppose we want to choose SMCLK as the clock source.The command is as follows

//TACTL=TASSEL_2//; // 10 =>SMCLK
 * //DIVIDER/1 **ID**(Internal Divider) bits ---//

//00 => /1//

//01 => /2//

//10 => /4//

//11 => /8//

Suppose we want a factor of 4. The command is as follows //://

//TACTL =ID_2;//


 * MODE Control : **MC** bits //---//

//00 => Stop Mode//

//01 => Up Mode//

//10 => Continuous Mode//

//11 => Up/Down Mode//


 * Interrupt Flag : **TAIFG** bit

//0 => No Interrupt pending//

//1 => Interrupt pending//


 * TAR register setting :**

The **TAR** register is the count of TIMER A. It can be read any time to see the current value of Timer A and a certain task can be performed at that point of time. //TACCR register setting :// In compare mode (we are currently discussing compare mode), it holds the value of the count entered by the user for comparison to the timer value in the Timer A register.

//**__EXAMPLE CODE__** : (//__toggle led without using interrupts__//)//

//#include"msp430g2452.h"// //void main(void)// //{// //WDTCTL = WDTPW + WDTHOLD;// //stop watchdog timer// //unsigned int x;// //P1DIR=0x01;//

/***clock selection, divider selection,mode selection***/ /***compare value to be decided by user****/**

/ reset timer parameters**/**
 * while(1)**
 * if(timer value >= compare value)**
 * /***Toggle led**/**
 * /** clear timer parameters/
 * /***Toggle led**/**
 * /** clear timer parameters/
 * }**
 * }**
 * }**

/*__clock selection, divider selection,mode selection__***/** TACTL=TASSEL_2 + MC_2 + ID_3; //we have chosen SMCLK with a divider of 4 and continuous mode//


 * /***//__compare value to be decided by user__///
 * //x=1000;//**
 * //if(timer value >= compare value)//**
 * //if(TAR>=x)//**

///**__Toggle led__**///
 * //P1OUT^=0x01;//**

/***__//clear timer parameters//__*****/** //TACTL|=BIT2;// TACLR is bit 2.setting this bit resets TAR, clock divider and direction

TACTL=TASSEL_2 + MC_2 + ID_3;//
 * /***__reset timer parameters__**/**

**//FULL CODE ://**
//#include"msp430g2452.h"// //void main(void)// //{// //WDTCTL = WDTPW + WDTHOLD;// //P1DIR=0x01;// //unsigned int x;// //TACTL=TASSEL_2 + MC_2 + ID_3;// //x=1000;// //while(1)// //{// //if(TAR>=x)// //{// Stop WDT P1OUT^=0x01; TACTL|=BIT2; TACTL=TASSEL_2 + MC_2 + ID_3; } } }

This was a very basic code showing some basic settings I timer registers. We haven’t used TACCR register for comparing the count value in this example intentionally to show that the comparison can be done manually also using if else statements and loops.

**PWM outputs capability :**
The output unit is used to generate output signalssuch as PWM signals. Each output unit has 8 operating modes that generate signals The output modes are defined by the **OUTMOD** bits which will be shown later. The OUT signal is changed with the rising edge of of the timer clock. The 8 operating modes are as follows.Refer to the datasheet for more explanations.

//**Example**// : __//**Using Timer in Up mode**//__ : The OUT signal is changed whenever the counter counts up to the **TACCR** value and rolls from **TACCR** to zero, depending on the output mode.

We will be discussing one mode, say mode 7. There are two compare values namely **TACCR0** and **TACCR1.** SEE the picture above. The wave repeats itself after every **TACCR0** counts and it changes from high to low after **TACCR1** counts hence deciding the duty cycle of the wave. Suppose we want to have 50% duty cycle of wave. Simply we put the value of **TACCR1** equal to the half of the **TACCR0** value. __**NOTE**__ : please refer to the datasheet of your msp430 device to see the bits capable of producing the PWM outputs.
 * TACCR0** defines the __**Time period**__ of the required PWM signal.
 * TACCR1** defines the __**duty cycle**__ of the PWM signal.

__**EXAMPLE code**__ :

//#include // //void main(void)// //{// //WDTCTL = WDTPW +WDTHOLD;// /// define P1.2 bit for PWM output using PxSEL register ***/**// //P1DIR |= BIT2;// /// ***define an OUTPUT mode for the PWM wave***/// /// ***define a value of CCR0 for the time period of the output wave***//**/** //}//
 * /** //*define a value of CCR1 for the duty cycle of the output wave//**/**
 * /** //*define a clock and mode of operation for the timer//**/**
 * //_BIS_SR(LPM0_bits);// /**//*enter LPM0 low power mode commannd*///

//P1SEL |= BIT2;//
 * /**__//define P1.2 bit for PWM output using PxSEL register//__**/**

//CCTL1 = OUTMOD_7;//
 * /** //**__define an OUTPUT mode for the PWM wave__***//**/**

//CCR0 = 1024;//
 * /** //*__define a value of CCR0 for the time period of the output wave__//**/**


 * /** //**__define a value of CCR1 for the duty cycle of the output wave__**///
 * //CCR1 = 256;//**

/// **__define a clock and mode of operation for the timer__***///** //TACTL = TASSEL_2 + MC_1;// SMCLK,UP mode//

__**FULL code :**__
//#include // //void main(void)// //{// //WDTCTL = WDTPW +WDTHOLD;// stop watchdog timer P1SEL |= BIT2; P1DIR |= BIT2; //P1.2 output// //CCTL1 = OUTMOD_7;// CCR1 reset/set CCR0 = 1024; //PWM period// //CCR1 = 256;// CCR1 PWM duty cycles TACTL = TASSEL_2 + MC_1; //SMCLK up mode// //_BIS_SR(LPM0_bits);// enter LPM0 low power mode }//

__**NOTE**__ : by default, SMCLK is sourced at 1.1 MHz frequency. So with a divider of 1 and TACCR0 value of 1024 cycles. The time period of the output signal is 1024/(1.1 MHz) = 930 micro seconds And the duty cycle is 25% since CCR1 is one-fourth of CCR0 value. So we are having a PWM wave with a time period of 930 micro seconds and having a duty cycle of 25%.
 * Similarly, we can get waves of different frequencies by changing the frequency of the clock sources and divider factor and can vary the duty cycle as per our requirement